1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device and a method for fabricating the same, to improve the picture quality.
2. Discussion of the Related Art
With the recent development of high-technology image display apparatuses, such as high definition televisions, various types of flat panel display devices have been actively researched and developed. The various types of flat panel display devices include, for example, a liquid crystal display (LCD) device, an electro-luminescence display (ELD), a vacuum fluorescent display (VFD), and a plasma display panel (PDP). Among the various types of flat display devices, the LCD device has been most widely used due its advantageous characteristics of thin profile, light weight, and low power consumption. In effect, the LCD device has become a substitute for the Cathode Ray Tube (CRT). For example, LCD devices are being used in car-mounted monitors and as monitors for color televisions as well as laptop computers and pocket computers.
In general, the LCD device includes an upper substrate that is referred to as a color filter array substrate, a lower substrate that is referred to as a thin film transistor array substrate, and a liquid crystal layer. The lower and upper substrates are bonded to each other, and the liquid crystal layer having dielectric anisotropy is formed between the lower and upper substrates. The thin film transistor array substrate includes a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes formed in pixel regions, and a plurality of thin film transistors. The color filter array substrate includes a color filter layer and a common electrode.
The plurality of gate lines on the thin film transistor array substrate are formed perpendicular to the plurality of data lines, to define a plurality of pixel regions. Also, each of the plurality of thin film transistor is formed adjacent to a crossing point of the gate and data lines such that each thin film transistor applies a data signal of the data line to each pixel electrode in response to a scanning signal of the gate line. A storage capacitor is formed with an adjacent gate line adjacent to the pixel electrode or an additional storage line such that the storage capacitor can maintain a voltage on the pixel electrode until the next scanning signal.
The storage capacitor maintains the voltage on the pixel electrode during a turn-off block of time for the corresponding thin film transistor as result of charge stored in the storage capacitor so as to prevent the picture quality from degrading when the thin film transistor is turned off. The storage capacitor can have a storage-on-common structure or a storage-on-gate structure. In the case of the storage-on-common structure, an additional electrode for the storage capacitor is formed. The additional electrode is connected to the common electrode. In the storage-on-gate structure, some area of the (n−1)th adjacent gate line is used as the electrode for the storage capacitor of the nth pixel region.
A related art LCD device and a method for fabricating the same will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is a plan view of an LCD device according to the related art. FIG. 2 is an equivalent circuit diagram of a unit pixel according to the related art. FIG. 3 is an expanded plan view of a repair area according to the related art.
The related art LCD device includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The liquid crystal layer is formed between the thin film transistor array substrate and the color filter array substrate, which are bonded to each other. As shown in FIG. 1, the thin film transistor array substrate includes a plurality of gate lines Gn 12, a gate insulating layer (not shown), data lines 15, thin film transistors TFTs, a passivation layer (not shown), a pixel electrode 17, a capacitor electrode 17a, and a C-shaped repair pattern 20. The plurality of gate lines Gn 12 transmit scanning signals. A gate insulating layer (not shown) is formed over the entire surface of the thin film transistor array substrate including the gate lines Gn 12. The data lines 15 are for transmitting video signals and are formed in a direction perpendicular to the gate lines Gn 12. Each of the thin film transistors TFTs is formed adjacent to where one of the gate lines 12 and one of the data lines 15 cross. A passivation layer (not shown) is formed over the entire surface of the thin film transistor array substrate including the thin film transistors TFTs.
In each pixel region, the pixel electrode 17 for the pixel region is electrically connected via a drain electrode 15b to the thin film transistor TFT of the pixel region. The capacitor electrode 17a, which generates a storage capacitance, is formed by the capacitor electrode 17a portion of the pixel electrode 17 overlapping the adjacent gate line Gn-1 12. The C-shaped repair pattern 20 has both ends overlapped by the data line 15 and a middle portion overlapped by the pixel electrode 17 of an adjacent pixel region. The C-shape repair pattern 20 is formed such that the data line 15 can be repaired if the data line 15 has defects or is disconnected.
Each of the thin film transistors TFTs include a gate electrode 12a, a gate insulating layer (not shown) a semiconductor layer 14, a source electrode 15a, and a drain electrode 15b. The gate electrode 12a is a portion of the gate line 12. The gate insulating layer (not shown) is formed over the gate electrode 12a. The semiconductor layer 14 is formed over the gate insulating layer above the gate electrode 12a. The source electrode 15a, which is fabricated along with the data line 15, overlaps one side of the semiconductor layer 14. The drain electrode 15b is formed at a predetermined interval from the source electrode on the other side of the semiconductor layer 14. In this case, the semiconductor layer 14 is formed in an island-shape above the gate electrode 12a. The semiconductor layer 14 can be extended beyond the outer sides of the data line 15 as well as over the gate electrode 12a. 
The repair pattern 20 is formed in the same layer as the gate line 12. If the predetermined portions of the data line 15, overlapping both ends of the repair pattern 20, are disconnected by tests for line defects and point defects or are otherwise determined to be defective, a laser can be irradiated onto the predetermined portions of the data line 15, overlapping both ends of the repair pattern 20, to repair the data line 15. More specifically, the laser irradiation electrically connects the repair pattern 20 to the data line 15 so as to rewire around any defects or openings in the data line 15.
As shown in FIG. 3, the data line 15 overlaps both ends of the repair pattern 20. The data line 15 has protrusions that improve the success of connecting the data line 15 to the repair pattern 20 with a laser. The protrusions of the data line 15 overlap both ends of the repair pattern. Further, the protrusions of the data line 15 have optical compensation patterns A to prevent over-etching of the corners of the protrusion. The repair pattern 20 has optical compensation patterns B at both ends of the repair pattern 20 to prevent over-etching of the corners of the ends of the repair pattern 20 and that also improve the success of connecting the data line 15 to the repair pattern 20 with a laser.
The storage capacitor Cst represented in FIG. 2 includes the storage electrode 17a, the adjacent gate line Gn-1 as well as a gate insulating layer and a passivation layer. More particularly, the gate insulating layer and the passivation layer are formed between the storage electrode 17a and the adjacent gate line Gn-1. The storage capacitor Cst maintains the pixel voltage during the time block when the thin film transistor is turned off.
The storage capacitor Cst has lower and upper electrodes with the gate insulating layer and the passivation layer between the lower and upper electrodes. The size of the storage capacitor may be changed by changing the size of the lower electrode, the size of the upper electrode or the thickness of the insulating layer. However, other voltages of the thin film transistor array substrate, as shown in FIG. 1 and FIG. 2, generate various parasitic capacitances Cdp, Cpr, Cdr1, Cdr2, and Cdr3 in addition to the capacitance across the liquid crystal Clc and the storage capacitance Cst.
As shown in FIG. 1 and FIG. 2, Cdp is the parasitic capacitance generated in the predetermined interval between the data line 15 and the pixel electrode 17. Cpr, Cdr1, Cdr2, and C1 are the parasitic capacitances generated by the repair pattern 20, which are generated when the data signal is transmitted through the repair pattern 20. More specifically, Cpr is the parasitic capacitance generated by the pixel electrode 17 and the portion of the repair pattern 20 overlapped by the pixel electrode 17. Also, Cdr1 and Cdr2 are the parasitic capacitances generated by the data line 15 overlapping the portions of the repair pattern 20. C1 is the parasitic capacitance generated in the interval between the data line 15 and the repair pattern 20.
The repair pattern 20 is formed in the same layer as the adjacent gate line Gn-1 and is also formed adjacent to the adjacent gate line Gn-1. Typically, when a voltage is not directly applied to the repair pattern 20, there are no parasitic capacitances between the repair pattern 20 and the data line 15. However, if a voltage of about 25V is applied to the adjacent gate line Gn-1, a voltage can be induced into the repair pattern 20. Thus, parasitic capacitances can be generated between the repair pattern 20 and the data line 15 when a large voltage is applied to an adjacent gate line Gn-1 of a pixel region.
A parasitic capacitance may cause a D.C. voltage offset to an A.C. voltage applied to the liquid crystal layer, ΔVp, thereby generating flicker, image sticking, and non-uniformity of luminance in the images. In other words, ΔVp changes will depend upon the parasitic capacitance for a pixel region when the gate voltage is changed from Vgh to Vgl, as shown in the following equation.
      Δ    ⁢                  ⁢    Vp    =                    (                  Cdp          +          Cpr          +                      Cdr            ⁢                                                  ⁢            1                    +                      Cdr            ⁢                                                  ⁢            2                    +                      C            ⁢                                                  ⁢            1                          )                              (                      Cdp            +            Cpr            +                          Cdr              ⁢                                                          ⁢              1                        +                          Cdr              ⁢                                                          ⁢              2                        +                          C              ⁢                                                          ⁢              1                                )                +        Cst        +        Clc              ⁢          (              Vgh        -        Vgl            )      As the parasitic capacitance increases, the effect on the voltage difference ΔVp of the liquid crystal layer also increases to the point that the picture image may become unstable.
In order to decrease parasitic capacitance Cdp generated between the data line 15 and the pixel electrode 17, the distance between the pixel electrode 17 and the data line 15 can be increased. However, in case of decreasing the pattern width of the pixel electrode 17 to increase the distance between the data line and the pixel electrode, the aperture ratio will be lowered. Decreasing the pattern width of the pixel electrode 17 to increase the distance between the pixel electrode and the data line in a high-definition display device is impractical since the quality of a high-definition display device is very dependent on the aperture ratio.
The size of both ends of the repair pattern can be decreased to reduce the parasitic capacitance Cdr1 and Cdr2 generated by the repair pattern 20. However, the dimensions of the ends of the repair pattern 20 overlapped the data line 15 can only be diminished to a certain degree. More particularly, the dimensions of the ends can only be reduced to a point where the repair success ratio still remains acceptable.
The optical compensation patterns A and B of FIG. 3 are provided to prevent corners from being overly decreased by an over-etch. More specifically, the optical compensation pattern A is formed on a protrusion of the data line 15 where the repair pattern 20 crosses under the data line 15. For reference, the size of the optical compensation pattern may be changed to a scanning direction by exposure.
The related art LCD device has several disadvantages. First, the voltage difference ΔVp increases due to the parasitic capacitance generated by the repair pattern. As a result, malfunctions appear in the display at pixel regions in which such parasitic capacitance occurs. Secondly, parasitic capacitance is additionally formed by the optical compensation patterns A and B where the optical compensation patterns A are formed on the protrusion of the data line and where the optical compensation patterns B are formed on both ends of the repair pattern. Third, the insulating layers formed between the repair pattern and the data line may not be uniformly consistent or aligned. Accordingly, the deviations in parasitic capacitance amongst the pixel regions may be generated due to such misalignments or inconsistencies such that it is impossible to realize a uniform luminance across the picture image.